DVS for EML

The FM model of the H2VMU of DVS for EML
The FM model of the HDD Unit of DVS for EML
The CCSM Board
The PCDM Board
The WCM Board
The CWCM Board
An overview of the H2VMU with the DVS boards

This Digital Video System (DVS), based on an evolution of TSD’s H2VMU platform, was specifically designed for Scientific Payloads on board the International Space Station (ISS).

It represents a mature, robust and effective solution offering to the ISS Users a very wide range of possibilities, in terms of video resolution & frame rate and real-time image processing/compression, and it is able to fulfill the increasingly demanding requirements of the image diagnostics.

The DVS  has been adopted for the EML facility on board the ISS (material science experiment to be flown in  Spring 2014). It comprises a ground and a flight segment.

 DVS FLIGHT SEGMENT

The DVS flight segment is able to:

 
  • receive the images coming from the camera
  • perform the real-time lossy compression of the images allowing the User to receive     on Ground the live video of the experiment
  • store the compressed science video data on a non volatile memory (HDD Unit)
  • transmit the compressed/uncompressed images via SpaceWire to EDR
  • command/data exchange with on-board computer of the facility
  • synchronize the on-board time with the facility time

The DVS flight segment is composed of:

 
  • one High-Resolution High-Frame Rate Video Management Unit (H2VMU)
  • one Hard-Disk (HDD) unit (composed of an HDD crate and HDD drawer)
EML DVS Main Specifications
Video Input
  • up to 60Mpixel/s
  • 8, 10 or 12 bit/pixel resolution

Compression Algorithm
  • Lossless and lossy DWT compression by using EZT algorithm with 9/7 integer filter

Custom Processing Resources
  • four Virtex4 LX60 able to operate independently or in parallel

Storage Capacity
  • Up to 250 GBytes

Storage Data Rate
  • Up to 1 Gb/s

Interfaces
  • 1 x CameraLink interface for the reception of the video data
  • 1 x RS422 asynchronous interface for the exchange of commands and status data (nominal operating mode)
  • 2 x HSSL interfaces for the dispatch of the video data
  • 2 x opto-coupled inputs allowing the unit to receive the Time Synch pulse and Power on/off commands
  • 1 x 28V power input from the facility
  • 4 x interfaces to PT1000 sensors for temperature monitoring
  • 1 x CAN Bus I/F and local display for health-check

Power Input Interface characteristics
  • Input Voltage (continuous): 22¸36 [V]
  • Input Current: 1.65 A @ 28Vdc
  • Hardwired under and over voltage protection, over-current protection and inrush current limiter

Mass
  • H2VMU: 6550 [g]
  • HDD Unit: 2150 [g]

Size
  • H2VMU:114 x 255 x 187 [mm]
  • HDD Unit: 140 x 82 x 220 [mm]

Environment
  • Operating temperature: 0¸50 [°C]
  • Non-Operating temperature: -20¸60 [°C]

 

H2VMU ARCHITECTURE

 

Control Configuration & Storage Module (CCSM)

  • dedicated to the entire DVS control, communication and storage management
  • processor (IBM PPC750CL  PowerPC) and FPGA based architecture
  • main FPGA for configuration & status data transfer; two secondary FPGAs for video data formatting, routing and PCI/PCI-X communication to the Host Bridge
  • antifuse FPGA for power supervision and latch-up protection
  • SDRAM for buffering of video data
  • 6 Channel-Link Interface for communication with CWCM/WCM boards
  • redundant CAN Bus network for low-speed communication with H2VMU boards
  • 2 x SpaceWire I/F (up to 50 Mb/s in nominal configuration)
  • 1 x SATA I/F Towards HDD Unit (transfer rate up to 300 MB/s)
  • HK data sample rate: 10Hz
  • conduction cooled and  double europe size

 

Camera I/F and Wavelet Compression Module (CWCM)

  • dedicated to the image grabbing from the Camera and video pre-processing/compression
  • FPGA based architecture (Video front-end FPGA plus Antifuse FPGA for power supervision
  • and latch-up protection)
  • image pre-processing (binning, resizing, etc.)
  • lossy Wavelet compression
  • SDRAM Buffer for wavelet compressor
  • 4 x Channel-Link Interface for communication with WCM/CCSM board
  • 1 x Camera Link Interface towards external camera
  • redundant CAN Bus network for low-speed communication with CCSM board Video Front-End FPGA
  • pixel-rate: 60 Mpixel/s; Video Pixel quantization: 8, 10, 12 bits
  • conduction cooled and double europe size

 

Wavelet Compression Module (WCM)

  • dedicated to Wavelet compression or Custom processing
  • FPGA based architecture (4 x Wavelet compressor FPGA plus Antifuse FPGA for power supervision and latch-up protection)
  • SDRAM Buffers for wavelet compressor
  • 2 x Channel-Link Input Interface
  • 4 x Channel-Link Output Interface
  • Redundant CAN Bus network for low-speed communication with CCSM board
  • DWT CORE for wavelet image transform; Wavelet Filters: 9/7; Quantizer: Enhanced EZW
  • input data-rate: up to 60Mpixel/s
  • compression factor: from lossless to 100
  • conduction cooled and double europe size 

 

Power Conditioning & Distribution Module (PCDM)
  • dedicated to power conditioning & management for H2VMU and HDD and to HK data collection
  • anti-fuse FPGA based architecture
  • built-In Latch-up protection circuits for HDD and the H2VMU modules
  • hardwired under and over voltage protection, over-current protection and inrush current limiter
  • A/D converter resolution: 12 bits; Acquisition Rate: 10Hz
  • conduction cooled and  double europe size