Overall OBC Unit Mechanical Layout

 The OBC (On Board Computer) developed by TSD is a general purpose space computing platform based on LEON3 FT processor and represents the core element of an OBDH. It provides a set of standard services for space platforms:

  • Computational resources for the flight application software

  • CCSDS TM packetization and TC decoding

  • Communication with the Payload by means of different interfaces (SpaceWire, CAN Bus, RS-422 serial asynchronous I/F)

  • Time management

Furthermore the OBC can host a mezzanine board that accommodates additional controllers & interfaces towards the TM/TC Transmitter and Receiver, the AOCS and the GNC subsystems and provides an FPGA-based hardware accelerator for intensive data processing algorithms. It is possible also to provide Reed Solomon, convolutional and pseudo-randomization encoding and authentication Layer for TC




The board is based on two identical sections that can be configured:

  • in cold redundancy to provide high reliability, or
  • in master-slave mode, so to run in parallel to improve processing capabilities

The two sections have independent power supplies lines that can be switched off by the PCDM (Power Conditioning and Distribution Module) that is a stacked module in the same OBC unit.

Each of the two sections is based on a complex System-On-Chip built around the LEON3 fault-tolerant embedded CPU in an Actel FPGA (flash-based RT3PE3000L or antifuse RTAX2000).

The processor program memory includes:

  • the boot PROM for the BIOS and the OS image
  • the EEPROM for the application software

Both are EDAC protected to correct bit-flip due to SEU. The EEPROM can be reprogrammed in field, so to support software upload. The data memory is based on SDRAM devices with EDAC protection. A NAND flash is also foreseen to store the configuration data for the FPGAs of the mezzanine card. The Actel FPGA embeds all the memory controllers along with the IP core for the CAN and SpaceWire nodes. As shown in the block diagram, the internal CAN network is kept apart from the external one to provide fault isolation.

UART lines and the 10/100 Ethernet port are foreseen for test and debug purpose, to connect the software debugger on-ground and upload the application software during the test phases. The Ethernet interface, whose physical transceiver is not available in qualified version, is powered-off in flight mode – as it is unused in this case – to avoid any problem because of radiation effects.

Two ports are used for each section to receive the data coming from the mezzanine card. The data transmission is arbitrated with a simple request/grant scheme; the OBC mezzanine card sets the request line whenever has valid data to transmit and the mother board asserts the relevant grant line to start the transaction. During the transfer, the mother board can release the grant line to pause the transmission, in case it is not able to buffer the incoming data.

According to the chosen scenario, the two ports for each section can be used:

  • to receive in parallel the data coming from the two sections of the mezzanine card
  • to support cross-strapping in the connection between mother and mezzanine card

The incoming data are directly transferred to the data memory to unburden the CPU from any overhead in data reception.

Each section is powered by independent 5V power line. High-efficient switching point-of-load converters are then used to derive the local supply voltages needed by the electronic circuits; a synchronization signal can be used to reduce the relevant electromagnetic emission. Moreover, a power enable control, driven by the PCDM, allows the user to the power down each section without switching off the power input.

The accommodation on a single 6U board of a remarkable number of components and a very high density routing were possible thanks to the adoption of a very advanced PCB based on sequential multilayer in accordance to the ECSS, with 16 Layer, 3 sequences of drilling (L1/L10 - L11/L14 - L1/L14) and via in pad.


OBC Board Specifications


  • Architecture
  • FPGA based with the soft IP core CPU.
  • FPGA:
    • 2 x Actel flash-based RT3PE3000L FPGA or
    • 2 x Actel antifuse RTAX2000 FPGA
  • CPU:
    • Leon3 - 32 bit processor core implemented in each FPGA
  • Each CPU is provided with:
    • 128Mbyte SDRAM with EDAC
    • 1MByte EEPROM for Application Code
    • 1MByte PROM for Boot Code


(each section)

  • Redundant CAN Bus I/F
  • 1 x RS-644 LVDS SpaceWire up to 50 Mbit/s
  • 1 x Channel Link Deserializer inputs @ ~1.5Gbit/s
  • 1 x Channel Link Serializer output @ ~ 1.5 Gbit/s
  • 4 x RS-644 LVDS General Purpose Inputs and Outputs
  • 2 x RS422 Debug I/F
  • 1 x Ethernet I/F

Possibility to have a RS-422 TTC-B-01 I/F instead of the RS-644 I/F

Power Input

  • Input Voltage: 5 VDC


  • Input Current:  1.04 A


  • Power Consumption: 5.2W


  • 233 x 160 [mm] excluding frame


  • 259.5[g] excluding frame


  • Operating Temperature: -40÷80 [°C]


  • Non-Operating Temperature Range: -55÷125 [°C]

Radiation Tolerance

  • 10Krad, ITAR free version with low cost components
  • 100Krad, ITAR version